1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to interconnection layout of semiconductor memory devices having word lines and/or bit lines of a multi-layered interconnection structure.
2. Description of the Background Art
In dynamic random access memory (DRAM), a memory cell is comprised of a capacitor storing data and an access transistor for reading storage data, or stored electric charges in the capacitor on a bit line. The electric charges stored in the capacitor of the memory cell is read on the bit line and a voltage appearing on the bit line is amplified by a sense amplifier, to internally read the data stored in the memory cell.
The bit lines are arranged in a folded bit line arrangement, in which bit lines are arranged in pair on one side of the sense amplifier. In this folded bit line arrangement, a memory cell data is read on one of paired bit lines and the voltage of the other bit line is used as a reference voltage, and a corresponding sense amplifier differentially amplifies the voltages of the bit line pair to read the memory cell data.
Since the bit lines are arranged adjacently to each other in parallel, when noise is generated in a bit line pair, the noise is generated onto both of the paired bit lines in a common phase. Since the sense amplifier differentially amplifies the voltages of a corresponding bit line pair, such common phase noise can be cancelled and memory cell data can be sensed and amplified while eliminating an effect of the noise.
However, depending on storage data of selected memory cells, the voltages on bit lines of adjacent bit line pairs may vary in opposite directions in sensing operation. When this voltage variation is transmitted to an adjacent bit line through a capacitive coupling between bit lines, a bit line voltage varies to prevent accurate read out of memory cell data due to reduction in sensing margin or the change to reverse data.
In order to reduce an effect of noise due to parasitic capacitance between adjacent bit line pairs, a twisted bit line structure is proposed, for example, in Japanese Patent Laying-Open No. 11-87641, in which a bit line pair is provided with a crossing to reduce parasitic capacitance between the bit lines of adjacent bit line pairs.
According to the twisted bit line arrangement of the prior art document as described above, the bit lines in a pair are arranged in parallel on different interconnection layer using first and second metal interconnection lines with connection of the first and second metal interconnection lines exchanged at a predetermined portion, for implementing the twisted bit line structure. A memory cell is connected to the lower, first metal interconnection line.
In the above prior art document, an active region having a memory cell formed therein is provided with a bit line contact to positionally exchange the first and second metal interconnection lines to implement the twisted structure. Providing the twisting bit line contact in the active region can prevent an increase in area of a memory cell array that would be caused when a memory cell-free region is provided dedicatedly to a bit line contact.
In the prior art document, however, where a word line and a bit line are orthogonally arranged to each other, in order to connect the upper bit line to the lower bit line at the bit line twisting portion, the upper bit line is deviated positionally in the direction of the word line to assure a bit line contact region. Therefore, bit line spacing is reduced in the twist formation region, and a bit line pitch is determined by the spacing between bit lines in the twist region at an interlayer contacting region. Thus, if bit lines are arranged with a further reduced pitch according to shrinking of a memory cell, a sufficient interlayer contact region for the twisted bit line arrangement cannot be assured.
Further, in the prior art document, a bit line is arranged extending over the contact region for the twisted bit line arrangement, and a memory cell is connected to the protruding portion of the bit line, in order to use the active region more efficiently. However, bit lines of the lower layer on a common column are separated, and in the separation region a lithography dummy word line is arrange. A memory cell connected to the lithography dummy word line is not used for storing data. Therefore, in the bit line crossing region, the active region is not efficiently used.
Furthermore, in the prior art document, a word line is formed of an interconnection line below the first metal interconnection line for the bit line. As a word line structure, however, a word line structure of a single layer is used. As a word line structure for driving a word line to a selected state at high speed, a word line shunt structure or a hierarchical word line structure is normally employed. Therefore, if as a word line, a gate electrode line (a row select line) connecting to a gate of an access transistor of a memory cell and an upper shunting low-resistance metal interconnection line or a main word line are arranged, the first and second metal interconnection lines cannot be used for a bit line. The prior art document does not consider a combination of such a multi-layer word line of a word line shunt structure or a hierarchical word line structure and a twisted bit line structure.
The prior art document further fails to consider such a bit line structure that complementary bit lines are formed of interconnection lines of a common interconnection layer and an interconnection line of a different layer is used only at a twisted portion for positionally exchanging bit lines.
Furthermore, in a construction such as a system LSI having a semiconductor memory device and a logic integrated on a common semiconductor chip, the number of interconnection layers is limited to reduce a step between the semiconductor memory device and the logic. In a DRAM, there exist, as internal voltage, a large number of kinds of voltages such as a sense power supply voltage used by a sense amplifier, a high voltage transmitted to a selected word line, a bit line precharge voltage for precharging a bit line, a cell plate voltage transmitted to a cell plate of a capacitor of a memory cell, a substrate bias voltage applied to a substrate region of a memory cell array.
These voltages need to be supplied stably to corresponding circuit portions. As for the sense power supply voltage supplied to a sense amplifier, a sense power supply line is arranged in a meshed shape over a memory array. In the meshed shape sense power supply line arrangement, a sub sense power supply line is arranged in a word line shunt region in a row direction and connected to the sense power supply line in a sense amplifier band having sense amplifiers arranged therein. Therefore, this sense power supply line is not arranged over the memory array efficiently in a column direction.
An object of the present invention is to provide a semiconductor memory device having an internal interconnection layout allowing an array area to be used efficiently.
Another object of the present invention is to provide a semiconductor memory device having a twisted bit line arrangement implementing a reduced array area.
A still another object of the present invention is to provide a semiconductor memory device having a word line shunt structure and a twisted bit line arrangement implementing a reduced array area.
A further object of the present invention is to provide a semiconductor memory device having a multi-layer interconnection structure allowing memory cells to be arranged efficiently.
The semiconductor memory-device according to an aspect of the present invention includes a plurality of memory cells arranged in rows and columns and a plurality of row select lines arranged corresponding to the memory cell rows and each connecting to memory cells on a corresponding row. The memory cells include normal memory cells storing data and dummy cells for maintaining geometry of the normal memory cells. The row select line include a normal row select line connecting to the normal memory cells and a dummy row select line connecting to the dummy cells.
The semiconductor memory device according to one aspect of the present invention further includes a plurality of bit line pairs arranged corresponding to the memory cell columns and each connecting to memory cells on a corresponding column. The plurality of bit line pairs are each selectively have a crossing at a preallocated twisting regions, and in the twisting region, a row select line is arranged and a crossing is formed of an interconnection line above the row select line and bit line.
The semiconductor memory device according to the one aspect of the present invention further includes a plurality of low-resistive conductive lines arranged, in a region other than the twisting region in correspondence with the row select lines, extending in the row direction and electrically connected in a predetermined region to corresponding row select lines. The low-resistive conductive line is formed in an interconnection layer above the row select lines.
The semiconductor memory device according to the one aspect of the present invention further includes a connection line connecting the low-resistive conductive line in the predetermined region to a corresponding row select line. The connection line includes a first connection line for electrically connecting the row select line arranged in the twisting region and the corresponding low-resistive conductive line, and a second connection line for electrically connecting a normal row select line with the low-resistive conductive line arranged corresponding to a dummy row select line.
The semiconductor memory device according to another aspect of the present invention includes a plurality of memory cells arranged in rows and columns and a plurality of row select lines arranged corresponding to the memory cell rows and connecting to memory cells on corresponding rows. The plurality of memory cells include normal cells storing data and dummy cells arranged in a predetermined region The plurality of row select lines include a normal row select line and a dummy row select line. The dummy row select line is arranged in the predetermined region concentrately.
The semiconductor memory device according to the another aspect of the present invention further includes a plurality of low-resistive conductive lines provided corresponding to and above the plurality of row select lines, and a plurality of connection lines electrically connecting the plurality of low-resistive conductive lines with the normal row select line. The connection line includes a first connection line for electrically connecting a low-resistive conductive line arranged in the predetermined region to a normal row select line.
The semiconductor memory device according to a further aspect of the present invention includes a memory array having a plurality of memory cells arranged in rows and columns and storing data, and a plurality of bit line pairs arranged corresponding to the memory cell columns and each connecting to memory cells on a corresponding column. Each bit line pair includes first and second bit lines. The first and second bit lines selectively have a crossing in a predetermined region. The crossing portion has first and second interconnections arranged therein. The first and second bit lines outside the crossing region are formed of the first interconnection lines.
The semiconductor memory device according to the further aspect of the present invention further includes a plurality of row select lines arranged corresponding to the memory cell rows and each connecting to memory cells on a corresponding row. The plurality of row select lines are formed of interconnection lines below the interconnection layer of the first interconnection lines, and the plurality of row select lines include an externally accessible row select line formed in the predetermined region and connected to a row of memory cells arranged in the predetermined region.
Arranging a row select line in the bit line twisting region enables an effective usage of an array area, and increased storage capacity can be achieved without increase in array area. Furthermore, by arranging a low-resistive conductive line in correspondence to a dummy row select line and connecting the low-resistive conductive line to a normal row select line, a region for arranging an interconnection for word line shunt can be used as a region for arranging different interconnection lines. For example, even if a twisted bit line arrangement is implemented with an interconnection of the same layer as a word line shunting, low-resistive conductive line, a word line shunting interconnection can be arranged so as to avoid the bit line twisting region, and a word line can be lined (a row select line and a low-resistive conductive line can be connected). A word line shunting structure and a twisted bit line arrangement can thus be implemented without increase in array area.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.